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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AT91SAM9G20 bảng dữ liệu(PDF) 47 Page - ATMEL Corporation |
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AT91SAM9G20 bảng dữ liệu(HTML) 47 Page - ATMEL Corporation |
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47 / 832 page  47 6384D–ATARM–04-May-09 AT91SAM9G20 Preliminary 11.3.9 New ARM Instruction Set . Note: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 11.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store multiple instructions LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRBT Load Register Byte with Translation STRBT Store Register Byte with Translation LDRT Load Register with Translation STRT Store Register with Translation LDM Load Multiple STM Store Multiple SWP Swap Word SWPB Swap Byte MCR Move To Coprocessor MRC Move From Coprocessor LDC Load To Coprocessor STC Store From Coprocessor CDP Coprocessor Data Processing Table 11-2. ARM Instruction Mnemonic List (Continued) Mnemonic Operation Mnemonic Operation Table 11-3. New ARM Instruction Mnemonic List Mnemonic Operation Mnemonic Operation BXJ Branch and exchange to Java MRRC Move double from coprocessor BLX (1) Branch, Link and exchange MCR2 Alternative move of ARM reg to coprocessor SMLAxy Signed Multiply Accumulate 16 * 16 bit MCRR Move double to coprocessor SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data Processing SMLAWy Signed Multiply Accumulate 32 * 16 bit BKPT Breakpoint SMULxy Signed Multiply 16 * 16 bit PLD Soft Preload, Memory prepare to load from address SMULWy Signed Multiply 32 * 16 bit STRD Store Double QADD Saturated Add STC2 Alternative Store from Coprocessor QDADD Saturated Add with Double LDRD Load Double QSUB Saturated subtract LDC2 Alternative Load to Coprocessor QDSUB Saturated Subtract with double CLZ Count Leading Zeroes |
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