AT91SAM9G20 datasheet(88/832 Pages) ATMEL

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6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

14.3

Functional Description

14.3.1

Reset Controller Overview

The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State

Manager. It runs at Slow Clock and generates the following reset signals:

• proc_nreset: Processor reset line. It also resets the Watchdog Timer.

• backup_nreset: Affects all the peripherals powered by VDDBU.

• periph_nreset: Affects the whole set of embedded peripherals.

• nrst_out: Drives the NRST pin.

These reset signals are asserted by the Reset Controller, either on external events or on soft-

ware action. The Reset State Manager controls the generation of reset signals and provides a

signal to the NRST Manager when an assertion of the NRST pin is required.

The NRST Manager shapes the NRST assertion during a programmable time, thus controlling

external device resets.

The startup counter waits for the complete crystal oscillator startup. The wait delay is given by

the crystal oscillator startup time maximum value that can be found in the section Crystal Oscil-

lator Characteristics in the Electrical Characteristics section of the product documentation.

The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con-

troller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on.

14.3.2

NRST Manager

The NRST Manager samples the NRST input pin and drives this pin low when required by the

Reset State Manager. Figure 14-2 shows the block diagram of the NRST Manager.

Figure 14-2. NRST Manager

14.3.2.1

NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low,

a User Reset is reported to the Reset State Manager.

However, the NRST Manager can be programmed to not trigger a reset when an assertion of

NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.

External Reset Timer

URSTS

URSTEN

ERSTL

exter_nreset

URSTIEN

RSTC_MR

RSTC_SR

NRSTL

nrst_out

NRST

rstc_irq

Other

interrupt

sources

user_reset

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