TUSB3200 datasheet(45/93 Pages) TI

45 / 93 page

3–5

3.4.4

CODEC Port Interface Signals (I2S Modes) Over Recommended Operating Conditions

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

fSCLK

Frequency, SCLK

CL = 50 pF

(32)FS

(64)FS

MHz

tcyc

Cycle time, SCLK

CL = 50 pF, See Note 1

1/(64)FS

1/(32)FS

tpd

Propagation delay, SCLK falling edge to LRCLK and SDOUT

CL = 50 pF

tsu

Setup time, SDIN to SCLK rising edge

Hold time, SDIN from SCLK rising edge

NOTE 1: Worst case duty cycle is 45/55.

tsu

SCLK

LRCLK, SD_OUT

SD_IN

tpd

tcyc

Figure 3–5. I2S Mode Timing Waveforms

3.4.5

CODEC Port Interface Signals (General Purpose Mode) Over Recommended Operating

Conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

fCSCLK

Frequency, CSCLK

CL = 50 pF

0.125

MHz

tcyc

Cycle time, CSCLK

CL = 50 pF, See Note 2

0.040

µs

tpd

Propagation delay, CSCLK to CSYNC, CDATO, CSCHNE and

CRESET

CL = 50 pF

tsu

Setup time, CDATI to CSCLK

Hold time, CDATI from CSCLK

NOTE 2: The timing waveforms in Figure 3-6 show the CSYNC, CDATO, CSCHNE and CRESET signals generated with the rising edge of the

clock and the CDATI signal sampled with the falling edge of the clock. The edge of the clock used is programmable. However, the timing

characteristics are the same regardless of which edge of the clock is used.

tsu

CSCLK

CSYNC, CDATO,

CSCHNE, CRESET

CDATI

tpd

tcyc

Figure 3–6. General-Purpose Mode Timing Waveforms

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