TMS320F241FN datasheet(11/116 Pages) TI

11 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE†

RESET

STATE‡

DESCRIPTION

NO.

STATE‡

DATA AND ADDRESS BUS SIGNALS (CONTINUED)

104

103

101

Bit x of the 16 bit Address Bus

Bit x of the 16-bit Address Bus

A10

A11

A12

A13

A14

A15

CLOCK SIGNALS

XTAL1/CLKIN

PLL oscillator input pin.

Crystal input to PLL/clock source input to PLL.

XTAL1/CLKIN is tied to one side of a reference crystal.

XTAL2

Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a reference

crystal. This pin goes in the high-impedance state when EMU1/OFF is active low.

CLKOUT/IOPD0

116

I/O

Clock output. This pin outputs either the CPU clock (CLKOUT) or the watchdog

clock

(WDCLK).

The

selection

made

the

CLKSRC

bit

(bit 14) of the System Control and Status Register (SCSR). This pin can be used

as a GPIO if not used as a clock output pin.

TEST SIGNALS

TCK

JTAG test clock with internal pullup

TDI

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected

TDO

I/O

JTAG scan out, test data output (TDO). The contents of the selected register

(instruction or data) is shifted out of TDO on the falling edge of TCK.

TMS

JTAG test-mode select (TMS) with internal pullup. This serial control input is

clocked into the TAP controller on the rising edge of TCK.

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶ Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS

is enabled.

NOTE:

Bold, italicized pin names indicate pin function after reset.

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