TMS320F241FN datasheet(45/116 Pages) TI

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TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

peripherals

The integrated peripherals of the TMS320x24x are described in the following subsections:

D External memory interface (’F243 only)

D Event-manager (EV2) module

D Analog-to-digital converter (ADC) module

D Serial peripheral interface (SPI) module

D Serial communications interface (SCI) module

D Controller area network (CAN) module

D Watchdog (WD) timer module

external memory interface (’F243 only)

The TMS320F243 can address up to 64K

× 16 words of memory (or registers) in each of the program, data,

and I / O spaces. On-chip memory, when enabled, occupies some of this off-chip range. In data space, the high

32K words can be mapped dynamically either locally or globally using the global memory allocation register

(GREG) as described in the

TMS320C241/C242/C243 DSP Controllers CPU, System, Instruction Set, and

Peripherals Reference Guide (literature number SPRU276). Access to a data-memory location, that is mapped

as global, asserts the BR pin low.

The CPU of the TMS320F243 schedules a program fetch, data read, and data write on the same machine cycle.

This is because from on-chip memory, the CPU can execute all three of these operations in the same cycle.

However, the external interface multiplexes the internal buses to one address and one data bus. The external

interface sequences these operations to complete first the data write, then the data read, and finally the program

read.

The ’F243 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces

provide interface to memory and I/O, thereby maximizing system throughput. The full 16-bit address and data

bus, along with the PS, DS, and IS space-select signals, allow addressing of 64K 16-bit words in program, data,

and I/O space. Since on-chip peripheral registers occupy positions of data-memory space, the externally

addressable data-memory space is 32K 16-bit words.

I/O design is simplified by having I/O treated the same way as memory. I/O devices are accessed in the I/O

address space using the processor’s external address and data buses in the same manner as memory-mapped

devices.

The ’F243 external parallel interface provides various control signals to facilitate interfacing to the device. The

R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal

provides a timing reference for all external cycles. For convenience, the device also provides the RD and the

WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those

cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to

the ’F243.

The bus request (BR) signal is used in conjunction with other ’F243 interface signals to arbitrate external global

memory accesses. Global memory is external data memory space in which the BR signal is asserted at the

beginning of the access. When an external global memory device receives the bus request, it responds by

asserting the READY signal after the global memory access is arbitrated and the global access is completed.

The TMS320F243 supports zero-wait-state reads on the external interface. However, to avoid bus conflicts,

writes take two cycles. This allows the TMS320F243 to buffer the transition of the data bus from input to output

(or output to input) by a half cycle. In most systems, TMS320F243 ratio of reads to writes is significantly large

to minimize the overhead of the extra cycle on writes.

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