TLC320AC02IPM datasheet(23/84 Pages) TI

23 / 84 page

2–8

The first secondary frame-sync falling edge, therefore, occurs at the following time (see

equation 7):

Time to first secondary frame sync

B register value

(FCLK periods)

(7)

A register value

B register value (number of MCLK periods)

A register value

B register value

(number of SCLK periods)

Number of frame sync intervals using equation 8.

All master and slave primary frame sync intervals must occur within the time of equation 7.

Since 18 shift clocks are required for each frame sync interval, then the number of frame sync

intervals from equation 8 is:

Number of frame sync intervals

A register value

B register value

18 (SCLKs frame sync interval)

(8)

A register value

B register value

Number of devices, master and slave, in terms of f(MCLK) and fs.

Substituting the value from equation 5 for the A

× B register value product gives the total number

of devices, including the master and all slaves that can be used, for a given master clock and

sampling frequency. Therefore, using equation 9:

Number of devices

f(MCLK)

144

(9)

Number of devices, master and slave, if slave devices are reprogrammed.

Equation 9 does not include reprogramming the slave devices after the frame sync delay occurs.

So if programming is required after shifting the slave frame syncs by the FSD register, then the

total number of devices is given by equation 10 is:

Number of devices

f(MCLK)

288

(10)

Example of the maximum number of devices if the slave devices are reprogrammed assuming

the following values:

f(MCLK)

+ 10.368 MHz, fs + 8kHz

then from equation 10,

Maximum number of devices

+ 10.368 MHz

288 (8 kHz)

+ 4.5

therefore, one master and three slaves can be used.

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