TLC320AC02IPM datasheet(20/84 Pages) TI

20 / 84 page

2–5

ADC Conversion Result

DAC Input Data

Control and Device Parameter

Data

16 SCLKs

Frame-Sync Interval

(primary communication)

Frame-Sync Interval

(secondary

communication)

SCLK

DOUT

DIN

[ (B register)/2] FCLK Periods†

† The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the

B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync

signal goes from high to low on the next shift clock low-to-high transition after (B register/2) filter clock periods.

Figure 2–1. Functional Sequence for Primary and Secondary Communication

2.7

Number of Slaves

The maximum number of slaves is determined by the sum of the individual device delays from the

frame-sync (FS) input low to the frame-sync delayed (FSD) low for all slaves according to equation 1:

(n) / tp(FS – FSD) < 1/2 shift-clock period

(1)

Where:

n is the number of slave devices.

Example:

From equation 1 above, the number of slaves is given by equation 2:

(n)

v 1

x (SCLK period) x

tp(FS

* FSD)

(2)

assuming the master clock is 10.368 MHz and the shift clock is 2.5965 MHz and tp(FS – FSD) is 40 ns, then

according to equation 3, the number of slaves is:

2.5965 MHz

x 1

40 ns

+ 1000

192

+ 4.8

(3)

The maximum number of slaves under these conditions is four.

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