TLC320AC02IPM datasheet(71/84 Pages) TI

71 / 84 page

A–1

Appendix A

Primary Control Bits

The function of the primary-word control bits D01 and D00 and the hardware terminals FC0 and FC1 are

shown below. Any combinational state of D01, D00, FC1, and FC0 not shown is ignored.

CONTROL FUNCTION OF CONTROL BITS

BITS

TERMINALS

D01

D00

FC1

FC0

On the next falling edge of FS, the AIC receives DAC data D15 – D02 to DIN and

transmits the ADC data D15 – D00 from DOUT.

On the next falling edge of FS, the AIC receives DAC data D15 – D02 to DIN and

transmits the ADC data D15 – D00 from DOUT.

The phase adjustment is determined by the state of FC1 and FC0 such that on the

next rising edge of the next internal FS, the next ADC/DAC sampling time occurs later

by the number of MCLK periods equal to the value contained in the A

′ register. When

the A

′ register value is negative, the internal falling edge of FS occurs earlier.

On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

The phase adjustment is determined by the state of FC1 and FC0 such that on the

rising edge of the next internal FS, the next ADC/DAC sample time occurs earlier by

the number of MCLK periods determined by the value contained in the A

′ register.

When the A

′ register value is negative, the internal falling edge of FS occurs later.

On the next falling edge of the primary FS, the AIC receives DAC data D15 – D02 at

DIN and transmits the ADC data D15 – D00 from DOUT.

When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive

a secondary control word at DIN. The secondary frame sync occurs at 1/2 the

sampling time as measured from the falling edge of the primary FS.

On the next falling edge of FS, the AIC receives DAC data D15 – D02 to DIN and

transmits the ADC data D15 – D00 from DOUT.

The phase adjustment is determined by the state of D01 and D00 such that on the

next rising edge of FS, the next ADC/DAC sampling time occurs later by the number

of MCLK periods determined by the value contained in the A

′ register. When the A′

On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

The phase adjustment is determined by the state of D01 and D00. On the next rising

edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK

periods determined by the value contained in the A

′ register. When the A′ register

value is negative, the internal falling edge of FS occurs later.

On the next falling edge of FS, the AIC receives DAC data D15 – D02 to DIN and

transmits the ADC data D15 – D00 from DOUT.

When D00 and D01 are both high, the AIC initiates a secondary FS to receive a

secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling

time as measured from the falling edge of the primary FS.

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