SN54ACT8997, SN74ACT8997

SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES

SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

15

POST OFFICE BOX 655303

counter register description

The counter register (CNTR) is an 8-bit serial register and an associated 8-bit parallel-load up/down counter.

A reset operation forces all bits of the shift register to a logic 0 but does not affect the counter. The counter can

be preloaded with an initial value before counting begins, and the current value of the counter scanned out via

the shift register. The CNTR can be used to count events occurring on the secondary scan path(s) using the

DCI pin as a counter clock and can output interrupt signals via DCO when the count has reached its end value.

An internal signal, CE, is generated as a logic 0 when the count reaches its end value (i.e., 00000000 for count

down, 11111111 for count up). For any other count value, CE is a logic 1. Many of the features of the CNTR are

configured by a bit in the CTLR including:

Count direction up or down (control register bit 9; reset condition = count up).

Stop counting upon counting down to 00000000 (control register bit 8; reset condition = do not latch on zero).

Output CE signals at DCO (control register bits 5 and 6; reset condition = do not output CE at DCO).

Edge of DCI on which to trigger (control register bit 1; reset condition = positive edge).

Figure 7 shows the order of scan for the CNTR.

TDO

Bit 7

(MSB)

TDI or DTDI

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Figure 7. Counter-Register Bits and Order of Scan