SN54ACT8997, SN74ACT8997

SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES

SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

14

POST OFFICE BOX 655303

boundary-scan register/ID-bus register description

The boundary-scan register (BSR) is a 10-bit serial register that can be used to capture data appearing at

selected device inputs, force data through device outputs, and apply data to the device’s internal logic. The BSR

is made up of boundary-scan cells (BSCs). Table 8 lists the device signal for each of the 10 BSCs that comprise

the BSR. A reset operation does not affect the contents of the BSR.

Table 8. Boundary-Scan Register Bit Mapping

BIT

TERMINAL

NAME

SIGNAL DESCRIPTION

9

MCI

Master condition in

8

MCO

Master condition out

7

DCI

Device condition in

6

DCOTS†

Enable control for DCO in 3-state configuration (active low)

5

DCOOD†

Enable control for DCO in open-drain configuration (active low)

4

DCO

Device condition out

3

ID4

Identification bus bit 4

2

ID3

Identification bus bit 3

1

ID2

Identification bus bit 2

0

ID1

Identification bus bit 1

† This internal signal cannot be observed from the I/O terminals of the device.

The four BSCs connected to the ID(1– 4) terminals form a subset of the BSR called the ID-bus register (IDBR).

The IDBR can be scanned without accessing the remaining BSCs of the BSR. Figure 5 shows the order of scan

for the BSR and IDBR.

Bit 9

(MSB)

TDI or DTDI

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

TDO

TDI or DTDI

IDBR

BSR

Figure 5. Boundary-Scan Register Bits and Order of Scan

bypass register description

The bypass register (BR) is a 1-bit serial register. The BR provides a means of effectively removing the

’ACT8997 from the primary scan path when it is not needed for the current test operation. Any selected

secondary scan paths remain active in the primary scan path as described in the data flow description. At power

up, the BR is placed in the scan path. During Capture-DR, the BR is preloaded with a low logic level. Figure 6

shows the order of scan for the bypass register.

TDO

TDI or DTDI

Bit 0

Figure 6. Bypass-Register Bit and Order of Scan