M68HC08 datasheet(87/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

I/O Registers

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Internal Clock Generator Module (ICG)

$0038

Internal Clock Generator

Trim Register (ICGTR)

See page 90.

Read:

TRIM7

TRIM6

TRIM5

TRIM4

TRIM3

TRIM2

TRIM1

TRIM0

Write:

Reset:

10000000

$0039

ICG DCO Divider Control

See page 91.

Read:

RRRR

DDIV3

DDIV2

DDIV1

DDIV0

Write:

Reset:

0000

UUUU

$003A

ICG DCO Stage Register

(ICGDSR)

See page 91.

Read:

DSTG7

DSTG6

DSTG5

DSTG4

DSTG3

DSTG2

DSTG1

DSTG0

Write:

Reset:

Unaffected by reset

= Unimplemented

= Reserved

U = Unaffected

Addr.

Bit 7

654321

Bit 0

Figure 6-10. ICG I/O Register Summary (Continued)

Table 6-5. ICG Module Register Bit Interaction Summary

Condition

CMIE CMF CMON CS ICGON ICGS ECGON ECGS N[6:0] TRIM[7:0] DDIV[3:0] DSTG[7:0]

Reset

$15

$80

—

CMF = 1

—

(1)

—

CMON = 0

(0)

—

CMON = 1

—

(1)

—

CS = 0

—

(0)

—

CS = 1

—

(1)

—

ICGON = 0

(0)

—

ICGON = 1

—

(1)

—

ICGS = 0

—

(0)

—

ECGON = 0

—

(0)

—

ECGS = 0

—

(0)

—

IOFF = 1

—

(1)

—

EOFF = 1

—

(1)

—

(1)

N = written

(0)

—

TRIM = written

(0)

—

— Register bit is unaffected by the given condition.

0, 1 Register bit is forced clear or set, respectively, in the given condition.

0*, 1* Register bit is temporarily forced clear or set, respectively, in the given condition.

(0), (1) Register bit must be clear or set, respectively, for the given condition to occur.

us, uc, uw Register bit cannot be set, cleared, or written, respectively, in the given condition.

Freescale Semiconductor, Inc.

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