EX128-CS100 datasheet(22/49 Pages) ACTEL

22 / 49 page

eX Family FPGAs

1- 18

v4.3

eX Timing Model

Hardwired Clock

External Setup =

tINYH + tIRD1 + tSUD – tHCKH

0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns

Clock-to-Out (Pad-to-Pad), typical

=tHCKH + tRCO + tRD1 + tDHL

1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns

Routed Clock

External Setup =

tINYH + tIRD2 + tSUD – tRCKH

0.7 + 0.4 + 0.5 – 1.3= 0.3 ns

Clock-to-Out (Pad-to-Pad), typical

=tRCKH + tRCO + tRD1 + tDHL

1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns

Note: Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).

Figure 1-14 • eX Timing Model

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

INYH = 0.7 ns

IRD2 = 0.4 ns

IRD1 = 0.3 ns

Combinatorial

Cell

I/O Module

DHL = 2.6 ns

RD8 = 1.2 ns

RD4 = 0.7 ns

RD1 = 0.3 ns

PD = 0.7 ns

I/O Module

DHL = 2.6 ns

RD1 = 0.3 ns

RCO= 0.6 ns

I/O Module

INYH = 1.3 ns

ENZL= 1.9 ns

SUD = 0.5 ns

HD = 0.0 ns

SUD = 0.5 ns

HD = 0.0 ns

RCKH= 1.3 ns

(100% Load)

IRD1 = 0.3 ns

Cell

Routed

Clock

RD1 = 0.3 ns

RCO= 0.6 ns

HCKH= 1.1 ns

Cell

Hard-Wired

Clock

I/O Module

DHL = 2.6 ns

ENZL= 1.9 ns

EX128-CS100 bảng dữ liệu(PDF) 22 Page - Actel Corporation

EX128-CS100 bảng dữ liệu(HTML) 22 Page - Actel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

bảng dữ liệu tải về

Link URL