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CDCE62005 bảng dữ liệu(PDF) 24 Page - Texas Instruments

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tên linh kiện CDCE62005
Giải thích chi tiết về linh kiện  Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
PDF  76 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
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CDCE62005 bảng dữ liệu(HTML) 24 Page - Texas Instruments

Back Button CDCE62005 Datasheet HTML 20Page - Texas Instruments CDCE62005 Datasheet HTML 21Page - Texas Instruments CDCE62005 Datasheet HTML 22Page - Texas Instruments CDCE62005 Datasheet HTML 23Page - Texas Instruments CDCE62005 Datasheet HTML 24Page - Texas Instruments CDCE62005 Datasheet HTML 25Page - Texas Instruments CDCE62005 Datasheet HTML 26Page - Texas Instruments CDCE62005 Datasheet HTML 27Page - Texas Instruments CDCE62005 Datasheet HTML 28Page - Texas Instruments Next Button
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Address
Bits
(4)
Lastin /
Lastout
FirstIn /
FirstOut
SPI _LE
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_LE
SPI_CLK
SPI_MOSI
SPI_MISO
SPIMaster (Host)
SPI _LE
SPI _CLK
SPI_MOSI
SPI_MISO
SPISlave (CDCE 62005)
DeviceRegisterN
0
1
2
3
4
5
6
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SPIRegister
DataBits (28)
CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Figure 19. CDCE62005 SPI Communications Format
CDCE62005 SPI Command Structure
The CDCE62005 supports four commands issued by the Master via the SPI:
• Write to RAM
• Read Command
• Copy RAM to EEPROM – unlock
• Copy RAM to EEPROM – lock
Table 4 provides a summary of the CDCE62005 SPI command structure. The host (master) constructs a Write to
RAM command by specifying the appropriate register address in the address field and appends this value to the
beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first. The
host must issue a Read Command to initiate a data transfer from the CDCE62005 back to the host. This
command specifies the address of the register of interest in the data field.
Table 4. CDCE62005 SPI Command Structure
Data Field (28 Bits)
Addr Field
(4 Bits)
Register
Operation
NVM
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
9
8
7
6
5
4
3
2
1
0
3
2
1
0
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
2
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
3
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
4
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
5
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
6
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
0
7
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
8
Status/Control
No
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
Instruction
Read Command
No
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
A
A
A
1
1
1
0
Instruction
RAM EEPROM
Unlock
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Instruction
RAM EEPROM
Lock
(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
(1)
CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration can
only be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed
24
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