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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CDCE62005 bảng dữ liệu(PDF) 39 Page - Texas Instruments |
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CDCE62005 bảng dữ liệu(HTML) 39 Page - Texas Instruments |
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39 / 76 page  UniversalInputControl PN PP 6 1 0 Register 5 10 9 8 Register 6 12 7 SN SP PINV PRI_IN SINV SEC_IN 5.1 5.0 5.6 INBUFSELY INBUFSELX ACDCSEL 1 0 0 1.9V 1 0 1 1.2V 1 1 0 1.2V 1 1 1 1.2V Nominal Vbb Settings Vbb 1 mF Vbb 5.0 5.1 5.8,6.12 5.9,5.10 INBUFSELX INBUFSELY TERMSEL INVBB P N INV 0 0 X X OFF OFF OFF X X 1 X OFF OFF OFF X 1 0 0 ON ON ON X 1 0 1 ON ON OFF SWITCHStatus Settings 50 50 50 50 CDCE62005 www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008 Universal Input Buffers (UIB) Figure 24 shows the key elements of a universal input buffer. A UIB supports multiple formats along with different termination and coupling schemes. The CDCE62005 implements the UIB by including on board switched termination, a programmable bias voltage generator, and an output multiplexer. The CDCE62005 provides a high degree of configurability on the UIB to facilitate most existing clock input formats. Figure 24. CDCE62005 Universal Input Buffer Table 15 lists several settings for many possible clock input scenarios. Note that the two universal input buffers share the Vbb generator. Therefore, if both inputs use internal termination, they must use the same configuration mode (LVDS, LVPECL, or LVCMOS). If the application requires different modes (e.g. LVDS and LVPECL) then one of the two inputs must implement external termination. Table 15. CDCE62005 Universal Input Buffer Configuration Matrix PRI_IN CONFIGURATION MATRIX SETTINGS CONFIGURATION Register.Bit → 5.7 5.1 5.0 5.8 5.9 5.6 Bit Name → HYSTEN INBUFSELY INBUFSELX PRI_TERMSEL PRIINVBB ACDCSEL Hysteresis Mode Coupling Termination Vbb 1 0 0 X X X ENABLED LVCMOS DC N/A — 1 1 0 0 0 0 ENABLED LVPECL AC Internal 1.9V 1 1 0 0 0 1 ENABLED LVPECL DC Internal 1.2V 1 1 0 1 X X ENABLED LVPECL — External — 1 1 1 0 0 0 ENABLED LVDS AC Internal 1.2V 1 1 1 0 0 1 ENABLED LVDS DC Internal 1.2V 1 1 1 1 X X ENABLED LVDS — External — 0 X X X X X OFF — — — — 1 X X X X X ENABLED — — — — SEC_IN CONFIGURATION MATRIX SETTINGS CONFIGURATION Register.Bit → 5.7 5.1 5.0 6.12 5.10 5.6 Bit Name → HYSTEN INBUFSELY INBUFSELX SEC_TERMSEL SECINVBB ACDCSEL Hysteresis Mode Coupling Termination Vbb 1 0 0 X X X ENABLED LVCMOS DC N/A — Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link(s) :CDCE62005 |
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