CDCE62005 datasheet(6/76 Pages) TI

6 / 76 page

Interface and Control Block

Interface

Control

REF_SELECT

/Power_Down

/SYNC

EEPROM(DefaultConfiguration)

Device

Hardware

SPI_LE

SPI_CLK

SPI_MISO

SPI_MOSI

Register0

StaticRAM(DeviceRegisters)

Register1

Register2

Register3

Register4

Register5

Register6

Register7

Register8

Register0

Register1

Register2

Register3

Register4

Register5

Register6

Register7

CDCE62005

SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com

The CDCE62005 is a highly flexible and configurable architecture and as such contains a number of registers so

that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM

determine device configuration at all times. On power-up, the CDCE62005 copies the contents of the EEPROM

into the RAM and the device begins operation based on the default configuration stored in the EEPROM.

Systems that do not have a host system to communicate with the CDCE62005 use this method for device

configuration. The CDCE62005 provides the ability to lock the EEPROM; enabling the designer to implement a

fault tolerant design. After power-up, the host system may overwrite the contents of the RAM via the SPI (Serial

Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62005 during system

operation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM, if the EEPROM is

unlocked.

Figure 4. CDCE62005 Interface and Control Block

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