AT89C5131A-RDTUM datasheet(125/188 Pages) ATMEL

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125

4337K–USB–04/08

AT89C5130A/31A-M

Figure 21-6. Endpoint FIFO Configuration

21.3.2

Read Data FIFO

The read access for each OUT endpoint is performed using the UEPDATX register.

After a new valid packet has been received on an Endpoint, the data are stored into the FIFO

and the byte counter of the endpoint is updated (UBYCTLX and UBYCTHX registers). The firm-

ware has to store the endpoint byte counter before any access to the endpoint FIFO. The byte

counter is not updated when reading the FIFO.

To read data from an endpoint, select the correct endpoint number in UEPNUM and read the

UEPDATX register. This action automatically decreases the corresponding address vector, and

the next data is then available in the UEPDATX register.

21.3.3

Write Data FIFO

The write access for each IN endpoint is performed using the UEPDATX register.

To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and

write into the UEPDATX register. The corresponding address vector is automatically increased,

and another write can be carried out.

Warning 1: The byte counter is not updated.

Warning 2: Do not write more bytes than supported by the corresponding endpoint.

21.4

Bulk/Interrupt Transactions

Bulk and Interrupt transactions are managed in the same way.

UEPNUM

Endpoint 0

Endpoint 6

UEPSTA0

UEPCON0

UEPDAT0

UEPSTA6

UEPCON6

UEPDAT6

SFR registers

UEPSTAX

UEPCONX

UEPDATX

UBYCTH0

UBYCTL0

UBYCTH6

UBYCTL6

UBYCTHX

UBYCTLX

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