AT89C5131A-RDTUM datasheet(97/188 Pages) ATMEL

97 / 188 page

4337K–USB–04/08

AT89C5130A/31A-M

output data are shifted (Figure 19-4 and Figure 19-5). The clock phase and polarity should be

identical for the Master SPI device and the communicating Slave device.

Figure 19-4. Data Transmission Format (CPHA = 0)

Figure 19-5. Data Transmission Format (CPHA = 1)

Figure 19-6. CPHA/SS Timing

As shown in Figure 19-5, the first SCK edge is the MSB capture strobe. Therefore the Slave

must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to

start the transmission. The SS pin must be toggled high and then low between each byte trans-

mitted (Figure 19-2).

Figure 19-6 shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driv-

ing its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start

transmission signal. The SS pin can remain low between transmissions (Figure 19-1). This for-

mat may be preferable in systems having only one Master and only one Slave driving the MISO

data line.

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

Byte 1

Byte 2

Byte 3

MISO/MOSI

Master SS

Slave SS

(CPHA = 1)

Slave SS

(CPHA = 0)

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