AT89C5131A-RDTUM datasheet(100/188 Pages) ATMEL

100 / 188 page

100

4337K–USB–04/08

AT89C5130A/31A-M

Reset Value = 0001 0100b

Not bit addressable

19.3.5.2

Serial Peripheral Status Register (SPSTA)

The Serial Peripheral Status Register contains flags to signal the following conditions:

• Data transfer complete

• Write collision

• Inconsistent logic level on SS pin (mode fault error)

Table 19-4 describes the SPSTA register and explains the use of every bit in the register.

Table 19-4.

SPSTA Register

SPSTA - Serial Peripheral Status and Control register (0C4H)

CPHA

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle state (see CPOL).

Set to have the data sampled when the SCK returns to idle state (see CPOL).

SPR1

SPR2 SPR1 SPR0 Serial Peripheral Rate

000Reserved

00 1FCLK PERIPH/4

010 FCLK PERIPH/8

011FCLK PERIPH/16

100FCLK PERIPH/32

10 1FCLK PERIPH/64

110FCLK PERIPH/128

1 11Reserved

SPR0

Bit

Number

Bit Mnemonic

Description

SPIF

WCOL

SSERR

MODF

Bit Number

Bit

Mnemonic

Description

SPIF

Serial Peripheral data transfer flag

Cleared by hardware to indicate data transfer is in progress or has been approved by a

clearing sequence.

Set by hardware to indicate that the data transfer has been completed.

WCOL

Write Collision flag

Cleared by hardware to indicate that no collision has occurred or has been approved by a

clearing sequence.

Set by hardware to indicate that a collision has been detected.

SSERR

Synchronous Serial Slave Error flag

Set by hardware when SS is de-

asserted before the end of a received data.

Cleared by disabling the SPI (clearing SPEN bit in SPCON).

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