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AT89C5131A-RDTUM bảng dữ liệu(PDF) 16 Page - ATMEL Corporation

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AT89C5131A-RDTUM bảng dữ liệu(HTML) 16 Page - ATMEL Corporation

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4337K–USB–04/08
AT89C5130A/31A-M
Figure 5-4.
PLL Filter Connection
The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF.
5.3.2
PLL Programming
The PLL is programmed using the flow shown in Figure 5-5. As soon as clock generation is
enabled user must wait until the lock indicator is set to ensure the clock output is stable.
Figure 5-5.
PLL Programming Flow
5.3.3
Divider Values
To generate a 48 MHz clock using the PLL, the divider values have to be configured following
the oscillator frequency. The typical divider values are shown in Table 5-1.
Table 5-1.
Typical Divider Values
VSS
PLLF
R
C1
C2
VSS
PLL
Programming
Configure Dividers
N3:0 = xxxxb
R3:0 = xxxxb
Enable PLL
PLLEN = 1
PLL Locked?
LOCK = 1?
Oscillator Frequency
R+1
N+1
PLLDIV
3 MHz
16
1
F0h
6 MHz
8
1
70h
8 MHz
6
1
50h
12 MHz
4
1
30h
16 MHz
3
1
20h
18 MHz
8
3
72h
20 MHz
12
5
B4h
24 MHz
2
1
10h



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