HD64F2144B datasheet(23/546 Pages) RENESAS

23 / 546 page

Rev. 1.00 Jun.24, 2005 Page xxiii of xxxii

Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting.................... 214

Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................... 215

Figure 9.13 Timing of Overflow Flag (OVF) Setting................................................................. 216

Figure 9.14 OCRA Automatic Addition Timing ........................................................................ 217

Figure 9.15 Timing of Input Capture Mask Signal Setting......................................................... 218

Figure 9.16 Timing of Input Capture Mask Signal Clearing ...................................................... 218

Figure 9.17 FRC Write-Clear Conflict ....................................................................................... 220

Figure 9.18 FRC Write-Increment Conflict................................................................................ 221

Figure 9.19 Conflict between OCR Write and Compare-Match

(When Automatic Addition Function is Not Used).................................................. 222

Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match

(When Automatic Addition Function is Used) ........................................................ 223

Section 10 8-Bit Timer (TMR)

Figure 10.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1) .......................................... 228

Figure 10.2 Block Diagram of 8-Bit Timers (TMR_Y).............................................................. 229

Figure 10.3 Pulse Output Example ............................................................................................. 241

Figure 10.4 Count Timing for Internal Clock Input.................................................................... 242

Figure 10.5 Count Timing for External Clock Input (Both Edges) ............................................ 242

Figure 10.6 Timing of CMF Setting at Compare-Match ............................................................ 243

Figure 10.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 243

Figure 10.8 Timing of Counter Clear by Compare-Match ......................................................... 244

Figure 10.9 Timing of Counter Clear by External Reset Input................................................... 244

Figure 10.10 Timing of OVF Flag Setting.................................................................................. 245

Figure 10.11 Conflict between TCNT Write and Clear.............................................................. 249

Figure 10.12 Conflict between TCNT Write and Increment ...................................................... 250

Figure 10.13 Conflict between TCOR Write and Compare-Match ............................................ 251

Section 11 Watchdog Timer (WDT)

Figure 11.1 Block Diagram of WDT .......................................................................................... 258

Figure 11.2 Watchdog Timer Mode (RST/

NMI = 1) Operation.................................................265

Figure 11.3 Interval Timer Mode Operation............................................................................... 266

Figure 11.4 OVF Flag Set Timing .............................................................................................. 266

Figure 11.5 Output Timing of

RESO signal ...............................................................................267

Figure 11.6 Writing to TCNT and TCSR (WDT_0)................................................................... 268

Figure 11.7 Conflict between TCNT Write and Increment ........................................................ 269

Figure 11.8 Sample Circuit for Resetting System by

RESO Signal ...........................................270

Section 12 Serial Communication Interface (SCI and IrDA)

Figure 12.1 Block Diagram of SCI............................................................................................. 272

Figure 12.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 290

HD64F2144B bảng dữ liệu(PDF) 23 Page - Renesas Technology Corp

HD64F2144B bảng dữ liệu(HTML) 23 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL