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HD64F2144B bảng dữ liệu(PDF) 79 Page - Renesas Technology Corp |
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HD64F2144B bảng dữ liệu(HTML) 79 Page - Renesas Technology Corp |
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79 / 546 page ![]() Section 2 CPU Rev. 1.00 Jun.24, 2005 Page 47 of 510 REJ09B0241-0100 op op rn rm NOP, RTS ADD.B Rn, Rm MOV.B @(d:16, Rn), Rm rn rm op EA (disp) op cc EA (disp) BRA d:16 (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. |
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