HD64F2144B datasheet(95/546 Pages) RENESAS

95 / 546 page

Section 3 MCU Operating Modes

Rev. 1.00 Jun.24, 2005 Page 63 of 510

REJ09B0241-0100

3.2.3

Serial Timer Control Register (STCR)

STCR enables or disables register access and on-chip flash memory, and selects the input clock of

the timer counter.

Bit

Bit Name

Initial Value

R/W

Description

IICS*

R/W

2C Extra Buffer Select

Specifies bits 7 to 4 of port A as open-drain output

buffers. These pins are used to implement an I

interface only by software.

0: PA7 to PA4 are normal input/output pins.

1: PA7 to PA4 are input/output pins enabling bus

driving.

6, 5



All 0

R/W

Reserved

These bits should not be changed.

IICE

R/W

2C Master Enable

Enables or disables the CPU access to the PWMX

registers (DADRAH/DACR, DADRAL,

DADRBH/DACNTH, DADRBL/DACNTL), and SCI

registers (SMR, BRR, SCMR).

0: SCI_1 registers are accessed through an area

from H'(FF)FF88 to H'(FF)FF89 and an area from

H'(FF)FF8E to H'(FF)FF8F.

SCI_2 registers are accessed through an area

from H'(FF)FFA0 to H9'(FF)FFA1 and an area

from H'(FF)FFA6 to H'(FF)FFA7.

SCI_0 registers are accessed through an area

from H'(FF)FFD8 to H'(FF)FFD9 and an area from

H'(FF)FFDE to H'(FF)FFDF.

1: No are accessed through an area from

H'(FF)FF88 to H'(FF)FF89 and an area from

H'(FF)FF8E to H'(FF)FF8F.

PWMX registers are accessed through an area

from H'(FF)FFA0 to H'(FF)FFA1 and an area from

H'(FF)FFA6 to H'(FF)FFA7.

No registers are accessed through an area from

H'(FF)FFD8 to H'(FF)FFD9 and through an area

from H'(FF)FFDE to H'(FF)FFDF.

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