7721 datasheet(140/577 Pages) RENESAS

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TIMER A

7721 Group User’s Manual

8–21

8.4 Event counter mode

8.4.1 Setting for event counter mode

Figures 8.4.2 and 8.4.3 show an initial setting example for registers relevant to the event counter mode.

Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.

INTERRUPTS.”

Fig. 8.4.2 Initial setting example for registers relevant to event counter mode (1)

T The counter divides the count source frequency by (n + 1)

when counting down, or by (FFFF16 – n + 1) when counting up.

Continue to Figure 8.4.3

on next page.

Selecting event counter mode and each function

Timer Aj mode register (j = 2 to 4)

(Addresses 5816 to 5A16)

Pulse output function select bit

0: No pulse output

1: Pulse output

Count polarity select bit

0: Counts at falling edge of external signal.

1: Counts at rising edge of external signal.

Up-down switching factor select bit

0: Contents of up-down register

1: Input signal to TAjOUT pin

! : It may be either “0” or “1.”

Selection of event counter mode

Setting division ratio

Can be set to

“000016” to “FFFF16” (n).

(b15)

(b8)

Timer A2 register (Addresses 4B16, 4A16)

Timer A3 register (Addresses 4D16, 4C16)

Timer A4 register (Addresses 4F16, 4E16)

Setting up-down register

Up-down register (Address 4416)

Timer A2 up-down bit

Timer A3 up-down bit

Timer A4 up-down bit

Timer A2 two-phase pulse signal processing select bit

Timer A3 two-phase pulse signal processing select bit

Timer A4 two-phase pulse signal processing select bit

Set the corresponding up-down bit when the contents of

the up-down register are selected as the up-down

switching factor.

Set the corresponding bit to “1” when the two-phase pulse

signal processing function is selected for timers A2 to A4.

0: Countdown

1: Countup

0: Two-phase pulse signal processing

function disabled

1: Two-phase pulse signal processing

function enabled

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