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CLOCK GENERATING CIRCUIT

7721 Group User’s Manual

5–5

5.3 Stop mode

Stop mode is used to stop oscillation when there is no need to operate the central processing unit (CPU).

The microcomputer enters Stop mode when the STP instruction is executed.

Stop mode can be terminated by an interrupt request occurrence or the hardware reset.

5.3.1 Stop mode

When the STP instruction is executed, the oscillator stops oscillating. This state is called “Stop mode.”

In Stop mode, the contents of the internal RAM can be retained intact when Vcc (power source voltage)

is 2 V or more. Additionally, the microcomputer’s power consumption is lowered. It is because the CPU and

all internal peripheral devices using clocks f2 to f512 stop the operation.

Table 5.3.1 lists the microcomputer’s state and operation in and after Stop mode.

Table 5.3.1 Microcomputer’s state and operation in and after Stop mode

State and Operation

Item

Oscillation

φCPU, φ

Clock

φ1, f2 to f512

Timers A, B

Serial I/O

A-D converter

DMA controller

DRAM controller

Watchdog timer

Pins

By interrupt request

occurrence

By hardware reset

State in

Stop mode

Operation

after terminating

Stop mode

Stopped

Can operate only in event counter mode

Can operate only when an external clock is selected

Stopped

Stopped (Note)

Stopped

Retains the same state in which the STP instruction was executed

Supply of

φCPU and φ starts after a certain time measured by

Watchdog timer has passed.

Operates in the same way as hardware reset

Note: DRAM refresh is not performed because the refresh timer also stops.

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