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SH7721 bảng dữ liệu(PDF) 311 Page - Renesas Technology Corp

tên linh kiện SH7721
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 8
Interrupt Controller (INTC)
Rev. 3.00 Jan. 18, 2008 Page 249 of 1458
REJ09B0033-0300
8.3.2
Interrupt Control Register 0 (ICR0)
ICR0 is a register that sets the input signal detection mode of the external interrupt input pin NMI,
and indicates the input signal level at the NMI pin.
Bit
Bit Name
Initial
Value
R/W
Description
15
NMIL
0/1*
R
NMI Input Level
Sets the level of the signal input at the NMI pin. This bit
can be read from to determine the NMI pin level. This bit
cannot be modified.
0: NMI input level is low
1: NMI input level is high
14 to 9 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
NMIE
0
R/W
NMI Edge Select
Selects whether the falling or rising edge of the interrupt
request signal at the NMI pin is detected.
0: Interrupt request is detected on falling edge of NMI
input
1: Interrupt request is detected on rising edge of NMI
input
7 to 0
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note:
*
The initial value is 1 when NMI input is high, 0 when NMI input is low.



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