SH7721 datasheet(293/1524 Pages) RENESAS

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Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 231 of 1458

REJ09B0033-0300

• Remarks

An exception occurs when a DMA transfer is executed while an exception instruction address

described above is specified in the DMAC. Since the DMA transfer is performed

asynchronously with the CPU instruction operation, an exception is also requested

asynchronously with the instruction execution. For details on DMAC, refer to section 10,

Direct Memory Access Controller (DMAC).

7.3.3

General Exceptions (MMU Exceptions)

When the address translation unit of the memory management unit (MMU) is valid, MMU

exceptions are checked after a CPU address error has been checked. Four types of MMU

exceptions are defined: TLB miss exception, TLB invalid exception, TLB protection exception,

initial page write exception. These exceptions are checked in this order.

A vector offset for a TLB miss exception is defined as H'00000400 to simplify exception source

determination. For details on MMU exception operations, refer to section 4, Memory Management

Unit (MMU).

(1)

TLB miss exception

• Conditions

Comparison of TLB addresses shows no address match.

• Types

Instruction synchronous, re-execution type

• Save address

Instruction fetch: An instruction address to be fetched when an exception occurred

Data access: An instruction address where an exception occurs (a delayed branch instruction

address if an instruction is assigned to a delay slot)

• Exception code

An exception occurred during read: H'040

An exception occurred during write: H'060

• Remarks

• The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is

updated. The vector address for TLB miss exception is VBR + H'0400. To speed up TLB miss

processing, the offset differs from other exceptions.

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