SH7721 datasheet(281/1524 Pages) RENESAS

281 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 219 of 1458

REJ09B0033-0300

7.1.2

Exception Event Register (EXPEVT)

EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception

codes to be specified in EXPEVT are those for resets and general exceptions. These exception

codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of

EXPEVT can be re-written using the software.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 12



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

11 to 0

EXPEVT

R/W

12-bit Exception Code

Note:

Initialized to H'000 at power-on reset and H'020 at manual reset.

7.1.3

Interrupt Event Register (INTEVT)

INTEVT is assigned to address H'FFFFFFD8 and stores an exception code or a code which

indicates interrupt priority order. A code to be specified when an interrupt occurs is determined by

an interrupt source. (For details, see section 8.4.6, Interrupt Exception Handling and Priority.)

These exception and interrupt priority order codes are automatically specified by the hardware

when an exception occurs. INTEVT can be modified using the software. Only bits 11 to 0 of

INTEVT can be modified using the software.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 12



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

11 to 0

INTEVT



12-bit Exception Code

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