SH7721 datasheet(257/1524 Pages) RENESAS

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Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 195 of 1458

REJ09B0033-0300

Both reading and writing use the longword of the data array specified by the entry address and

way number. The access size of the data array is fixed at longword.

1 1 1 1 0 0 1 0

VPN: Virtual page number

Valid bit

Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)

ASID: Address space identifier

Don’t care bit

Address field

Data field

Address field

Data field

Address field

Data field

24 23

17 16

12 1110 9 8 7

17 16

12 1110 9 8 7

24 23

17 16

12 11

10 9 8 7

17 16

10 9 8 7

24 23

29 28

17 16

12 1110 9 8 7

8 7

65 4 3 2 1

0 0 0

VPN

1 1 1 1 0 0 1 0

1 1 1 1 0 0 1 1

(1) TLB Address Array Access

• Read Access

•

Write Access

(2) TLB Data Array Access

• Read/Write Access

* . . . . . . . . . . . . *

VPN

* . . . . . . . . . *

VPN

0 . . . . . . . 0 VPN 0 V

ASID

* . . . . . . . . . . . . *

VPN

* . . . . . . . *

W0 * . . . . . . . . . *

VPN

ASID

* . . . . . . . . . . . . *

VPN

* . . . . . . . . . . . *

PPN

XVX PR SZ CD SH X

PPN: Physical page number

PR:

Protection key field

Cacheable bit

SH:

Share status bit

VPN: Virtual page number

0 for read, don’t care bit for write

Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)

Valid bit

SZ:

Page-size bit

Dirty bit

Don’t care bit

Figure 4.14 Specifying Address and Data for Memory-Mapped TLB Access

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