SH7721 datasheet(236/1524 Pages) RENESAS

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Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 174 of 1458

REJ09B0033-0300

4.2

There are four registers for MMU processing. These are all peripheral module registers, so they

are located in address space area P4 and can only be accessed from privileged mode by specifying

the address.

The MMU has the following registers. Refer to section 37, List of Registers, for more details on

the addresses and access size of these registers.

• Page table entry register high (PTEH)

• Page table entry register low (PTEL)

• Translation table base register (TTB)

• MMU control register (MMUCR)

4.2.1

Page Table Entry Register High (PTEH)

The page table entry register high (PTEH) register residing at address H'FFFF FFF0, which

consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual address

at which the exception is generated in case of an MMU exception or address error exception.

When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case

the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the

ASID, software sets the number of the currently executing process. The VPN and ASID are

recorded in the TLB by the LDTLB instruction.

A program that modifies the ASID in PTEH should be allocated in the P1 or P2 areas.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 10

VPN



R/W

The Number of the Logical Page

9, 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

7 to 0

ASID



R/W

Address Space Identifier

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