SH7721 datasheet(210/1524 Pages) RENESAS | Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 148 of 1458

REJ09B0033-0300

3.5.13

Operand Conflict

When an identical destination operand is specified with multiple parallel instructions, data conflict

occurs. Table 3.34 shows the correspondence between each operand and registers.

Table 3.34

Correspondence between Operands and Registers

X-Memory

Load

Y-Memory

Load

6-Instruction

ALU

3-Instruction

Multiply

3-Instruction

ALU

Ax

Ix

Dx

Ay

Iy

Dy

Sx

Sy

Du

Se

Sf

Dg

Sx

Sy

Dz

A0

*

1

*

2

*

2

*

1

*

1

A1

*

1

*

2

*

1

*

1

*

2

*

1

*

1

M0

*

1

*

1

*

1

*

1

M1

*

1

*

1

*

1

*

1

X0

*

2

*

1

*

2

*

1

*

1

*

1

*

2

X1

*

2

*

1

*

1

*

1

*

2

Y0

*

2

*

1

*

2

*

1

*

1

*

1

*

2

DSP

Registers

Y1

*

2

*

1

*

1

*

1

*

2

Notes: 1. Registers available for operands

2. Registers available for operands (when there is operand conflict)

There are three cases of operand conflict problems.

• When ALU operation and multiply instructions specify the same destination operand (Du and

Dg)

• When X-memory load and ALU operation specify the same destination operand (Dx and Du,

or Dz)

• When Y-memory load and ALU operation specify the same destination operand (Dy and Du,

or Dz)

In these cases above, the result is not guaranteed.

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