SH7721 datasheet(202/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 140 of 1458

REJ09B0033-0300

Every time a logical shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically

updated in accordance with the operation result. In case of a conditional operation, they are not

updated even though the specified condition is true and the operation is executed. In case of an

unconditional operation, they are always updated in accordance with the operation result. The

definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit

result is:

1. Carry or Borrow Mode: CS[2:0] = B'000

The DC bit indicates the last shifted out data as the operation result.

2. Negative Value Mode: CS[2:0] = B'001

Bit 31 of the operation result is loaded into the DC bit.

3. Zero Value Mode: CS[2:0] = B'010

The DC bit is set to 1 when the operation result is zero; otherwise it is cleared to 0.

4. Overflow Mode: CS[2:0] = B'011

The DC bit is always cleared to 0.

5. Signed Greater Than Mode: CS[2:0] = B'100

The DC bit is always cleared to 0.

6. Signed Greater Than or Equal Mode: CS[2:0] = B'101

The DC bit is always cleared.

The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]

bits. See the negative value mode part above. The Z bit always indicates the same state as the DC

bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit

always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits, but it is

always cleared in this operation. So is the GT bit.

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