SH7721 datasheet(111/1524 Pages) RENESAS

111 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 49 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

R/W

Block

Specifies whether an exception, interrupt, or user

break is enabled or not.

0: Enables an exception, interrupt, or user break.

1: Disables an exception, interrupt, or user break.

The BL bit is set to 1 in reset or exception handling

state.

27 to 10



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.



R/W

M Bit

Q Bit

These bits are used by the DIV0S, DIV0U, and DIV1

instructions. These bits can be changed even in user

mode by using the DIV0S, DIV0U, and DIV1

instructions. These bits are undefined at reset. These

bits do not change in an exception handling state.

7 to 4

I3 to I0

All 1

R/W

Interrupt Mask

Indicates the interrupt mask level. These bits do not

change even if an interrupt occurs. At reset, these bits

are initialized to B'1111. These bits are not affected in

an exception handling state.

3, 2



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.



R/W

Saturation Mode

Specifies the saturation mode for multiply instructions

or multiply and accumulate instructions. This bit can be

specified by the SETS and CLRS instructions in user

mode.

At reset, this bit is undefined. This bit is not affected in

an exception handling state.

SH7721 bảng dữ liệu(PDF) 111 Page - Renesas Technology Corp

SH7721 bảng dữ liệu(HTML) 111 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL