SH7721 datasheet(490/1524 Pages) RENESAS

490 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 428 of 1458

REJ09B0033-0300

(3)

On-Chip Peripheral Module Request Mode

In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module.

Transfer request signals comprise the transmit data empty transfer request and receive data full

transfer request from the ADC set by CHCR0 to CHCR5 and the SCIF0, SCIF1, MMC, USBF,

SIM, SIOF0, SIOF1, and SDHI set by DMARS0/1/2, and the compare-match timer transfer

request from the CMT (channels 0 to 4).

When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,

NMIF = 0), a transfer is performed upon the input of a transfer request signal.

When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer

destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer

request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive

data register. These conditions also apply to the SIOF1, MMC, USBF, SIM, SIOF0, SIOF1, and

SDHI. When the ADC is set as the transfer request, the transfer source must be the A/D data

generated by the CMT (channels 0 to 4).

The number of the receive FIFO triggers can be set as a transfer request depending on an on-chip

peripheral module. Data needs to be read after the DMA transfer is ended, because data may be

remained in the receive FIFO when the receive FIFO trigger condition is not satisfied.

SH7721 bảng dữ liệu(PDF) 490 Page - Renesas Technology Corp