SH7721 datasheet(475/1524 Pages) RENESAS

475 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 413 of 1458

REJ09B0033-0300

10.3.4

DMA Channel Control Registers (CHCR_0 to CHCR_5)

CHCR are 32-bit readable/writable registers that control the DMA transfer mode.

Bit

Bit Name

Initial

Value

R/W

Descriptions

31 to 24



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

DMA Overrun

Selects whether DREQ is detected by overrun 0 or by

overrun 1. This bit is valid only in CHCR_0 and

CHCR_1. This bit is always reserved and read as 0 in

CHCR_2 to CHCR_5. The write value should always be

0: Detects DREQ by overrun 0

1: Detects DREQ by overrun 1

R/W

Transfer End Level

Specifies whether the TEND signal output is high active

or low active.

This bit is valid only in CHCR_0 and CHCR_1. This bit

is always reserved and read as 0 in CHCR2 to

CHCR_5. The write value should always be 0.

0: Low-active output of TEND

1: High-active output of TEND

21 to 18



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

Acknowledge Mode

Selects whether DACK is output in data read cycle or in

data write cycle in dual address mode.

In single address mode, DACK is always output

regardless of the specification by this bit.

This bit is valid only in CHCR_0 and CHCR_1. This bit

is always reserved and read as 0 in CHCR_2 to

CHCR_5. The write value should always be 0.

0: DACK output in read cycle (dual address mode)

1: DACK output in write cycle (dual address mode)

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