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SH7721 bảng dữ liệu(PDF) 473 Page - Renesas Technology Corp

tên linh kiện SH7721
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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SH7721 bảng dữ liệu(HTML) 473 Page - Renesas Technology Corp

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Section 10
Direct Memory Access Controller (DMAC)
Rev. 3.00 Jan. 18, 2008 Page 411 of 1458
REJ09B0033-0300
(6) Channel 5
• DMA source address register_5 (SAR_5)
• DMA destination address register_5 (DAR_5)
• DMA transfer count register_5 (DMATCR_5)
• DMA channel control register_5 (CHCR_5)
(7) Common
• DMA operation register (DMAOR)
• DMA extended resource selector 0 (DMARS0)
• DMA extended resource selector 1 (DMARS1)
• DMA extended resource selector 2 (DMARS2)
10.3.1
DMA Source Address Registers (SAR_0 to SAR_5)
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the next source address. When the data is
transferred from an external device with the DACK in single address mode, the SAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the source address
value. The initial value is undefined.



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