SH7721 datasheet(463/1524 Pages) RENESAS

463 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 401 of 1458

REJ09B0033-0300

9.5.10

Wait between Access Cycles

As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often

collides with the next data access when the read operation from devices with slow access speed is

completed. As a result of these collisions, the reliability of the device is low and malfunctions may

occur. This LSI has a function that avoids data collisions by inserting wait cycles between

continuous access cycles.

The number of wait cycles between access cycles can be set by bits IWW[2:0], IWRWD[2:0],

IWRWS[2:0], IWRRD[2:0], and IWRRS[2:0] in CSnBCR, and bits DMAIW[2:0] and DMAIWA

in CMNCR. The conditions for setting the wait cycles between access cycles (idle cycles) are

shown below.

1. Continuous accesses are write-read or write-write

2. Continuous accesses are read-write for different spaces

3. Continuous accesses are read-write for the same space

4. Continuous accesses are read-read for different spaces

5. Continuous accesses are read-read for the same space

6. Data output from an external device caused by DMA single transfer is followed by data output

from another device that includes this LSI (DMAIWA = 0)

7. Data output from an external device caused by DMA single transfer is followed by any type of

access (DMAIWA = 1)

9.5.11

Bus Arbitration

To prevent device malfunction while the bus mastership is transferred between master and slave,

the LSI negates all of the bus control signals before bus release. When the bus mastership is

received, all of the bus control signals are first negated and then driven appropriately. In this case,

output buffer contention can be prevented because the master and slave drive the same signals

with the same values. In addition, to prevent noise while the bus control signal is in the high

impedance state, pull-up resistors must be connected to these control signals.

Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released

immediately after receiving a bus request when a bus cycle is not being performed. The release of

bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even

when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be

performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot

be immediately determined whether or not bus mastership has been released by looking at the

CSn

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