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SH7721 bảng dữ liệu(PDF) 407 Page - Renesas Technology Corp

tên linh kiện SH7721
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 9
Bus State Controller (BSC)
Rev. 3.00 Jan. 18, 2008 Page 345 of 1458
REJ09B0033-0300
9.5.4
CSn Assert Period Expansion
The number of cycles from
CSn assertion to RD and WEn (BEn) assertion can be specified by
setting bits SW1 and SW0 in CSnWCR. The number of cycles from
RD and WEn (BEn) negation
to
CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to
an external device can be obtained. Figure 9.11 shows an example. A Th cycle and a Tf cycle are
added before and after an ordinary cycle, respectively. In these cycles,
RD and WEn (BEn) are not
asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this
prolongation is useful for devices with slow writing operations.
T1
CKIO
A25 to A0
CSn
RD/
WR
RD
D31 to D0
D31 to D0
WEn(BEn)
BS
Th
Read
Write
T2
DACKn*
Tf
Note: * The waveform for DACKn is when active low is specified.
Figure 9.11
CSn Assert Period Expansion



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