SH7713 datasheet(232/904 Pages) RENESAS

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Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 192 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

31 to 9



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

Single virtual memory mode

0: Multiple virtual memory mode

1: Single virtual memory mode

7, 6



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

5, 4

All 0

R/W

Random counter

A 2-bit random counter that is automatically updated

by hardware according to the following rules in the

event of an MMU exception.

When a TLB miss exception occurs, all of TLB entry

way corresponding to the virtual address at which

the exception occurred are checked. If all ways are

valid, 1 is added to RC; if there is one or more

invalid way, they are set by priority from way 0, in

the order way 0, way 1, way 2, way 3. In the event

of an MMU exception other than a TLB miss

exception, the way which caused the exception is

set in RC.



Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

TLB flush

Write 1 to flush the TLB (clear all valid bits of the

TLB to 0). When they are read, 0 is always returned.

R/W

Index mode

0: VPN bits 16 to 12 are used as the TLB index

number.

1: The value obtained by EX-ORing ASID bits 4 to 0

in PTEH and VPN bits 16 to 12 is used as the

TLB index number.

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