SH7713 datasheet(230/904 Pages) RENESAS

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Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 190 of 860

REJ09B0288-0150

The MMU has the following registers. Refer the section 23, List of Registers, for the addresses

and access size for these registers.

• Page table entry register high (PTEH)

• Page table entry register low (PTEL)

• Translation table base register (TTB)

• MMU control register (MMUCR)

5.2.1

Page Table Entry Register High (PTEH)

The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which

consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual address

at which the exception is generated in case of an MMU exception or address error exception.

When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case

the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the

ASID, software sets the number of the currently executing process. The VPN and ASID are

recorded in the TLB by the LDTLB instruction.

A program that modifies the ASID in PTEH should be allocated in the P1 or P2 areas.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 10

VPN



R/W

Number of Virtual Page

9, 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

7 to 0

ASID



R/W

Address space identifier

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