SH7713 datasheet(75/904 Pages) RENESAS

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Section 2 CPU

Rev.1.50 Aug. 30, 2006 Page 35 of 860

REJ09B0288-0150

2.3.1

General Registers

There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to

R7_BANK1, and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB)

bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or

R0_BANK1 to R7_BANK1) are accessed as general registers. R0 to R7 registers in the selected

bank are accessed as R0 to R7. R0 to R7 in the non-selected bank is accessed as R0_BANK to

R7_BANK by the control register load instruction (LDC) and control register store instruction

(STC).

In user mode, bank 0 is selected regardless of he RB bit value. Sixteen registers: R0_BANK0 to

R7_BANK0 and R8 to R15 are accessed as general registers R0 to R15. The R0_BANK1 to

R7_BANK1 registers in bank 1 cannot be accessed.

In privileged mode that is entered by a transition to exception handling state, the RB bit is set to 1

to select bank 1. In privileged mode, sixteen registers: R0_BANK1 to R7_BANK1 and R8 to R15

are accessed as general registers R0 to R15. A bank is switched automatically when an exception

handling state is entered, registers R0 to R7 need not be saved by the exception handling routine.

The R0_BANK0 to R7_BANK0 registers in bank 0 can be accessed as R0_BANK to R7_BANK

by the LDC and STC instructions.

In privileged mode, bank 0 can also be used as general registers by clearing the RB bit to 0. In this

case, sixteen registers: R0_BANK0 to R7_BANK0 and R8 to R15 are accessed as general

registers R0 to R15. The R0_BANK1 to R7_BANK1 registers in bank 1 can be accessed as

R0_BANK to R7_BANK by the LDC and STC instructions.

The general registers R0 to R15 are used as equivalent registers for almost all instructions. In

some instructions, the R0 register is automatically used or only the R0 register can be used as

source or destination registers.

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