SH7713 datasheet(228/904 Pages) RENESAS

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Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 188 of 860

REJ09B0288-0150

Physical Address Space: This LSI supports a 29-bit physical address space. As shown in figure

5.5, the physical address space is divided into eight areas. Area 1 is mapped to the on-chip

module control register area and on-chip memory area. Area 7 is reserved.

For details on physical address space, refer to section 12, Bus State Controller (BSC).

H'0400 0000

H'0800 0000

H'0C00 0000

H'1000 0000

H'1400 0000

H'1C00 0000

H'1FFF FFFF

H'1800 0000

Area 0

Area 1

(On-Chip module control

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

(Reserved Area)

H'0000 0000

Figure 5.5 External Memory Space

Address Transition: When the MMU is enabled, the virtual address space is divided into units

called pages. Physical addresses are translated in page units. Address translation tables in external

memory hold information such as the physical address that corresponds to the virtual address and

memory protection codes. When an access to area P1 or P2 occurs, there is no TLB access and the

physical address is defined uniquely by hardware. If it belongs to area P0, P3 or U0, the TLB is

searched by virtual address and, if that virtual address is registered in the TLB, the access hits the

TLB. The corresponding physical address and the page control information are read from the TLB

and the physical address is determined.

If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing

will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in

external memory is searched and the corresponding physical address and the page control

information are registered in the TLB. After returning from the handler, the instruction that caused

the TLB miss is re-executed. When the MMU is enabled, address translation information that

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