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tên linh kiện SH7713
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 3 DSP Operating Unit
Rev.1.50 Aug. 30, 2006 Page 123 of 860
REJ09B0288-0150
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
Note:
The DC bit is always updated as the carry/borrow flag for ‘PADDC’ and ‘PSUBC’
regardless of the CS[2:0] state.
• Overflow Protection
The S bit in SR is effective for any ALU fixed-point arithmetic operations in the DSP unit. See
section 3.5.11, Overflow Protection, for details.
3.5.5
ALU Integer Operations
Figure 3.14 shows the ALU integer arithmetic operation flow. Table 3.23 shows the variation of
this type of operation. The correspondence between each operand and registers is the same as
ALU fixed-point operations as shown in table 3.22.
31
31
39
Ignored
Cleared to 0
31
39
0
Source 1
0
Destination
ALU
DSR
39
0
Source 2
GT
Z
N
V DC
Guard
Guard
Guard
Figure 3.14 ALU Integer Arithmetic Operation Flow



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