SH7713 datasheet(160/904 Pages) RENESAS

tên linh kiện	SH7713

Giải thích chi tiết về linh kiện	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 120 of 860

REJ09B0288-0150

MOVX

MOVX & PADD

MA/DSP

PADD X0, Y0, A0

MOVX.W @(R4, R8), X0

MOVX.W @R4+, X0

Slot

Stage

Operation Sequence Example

Addressing

Previous cycle result is used.

Figure 3.10 Operation Sequence Example

Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are

basically updated in accordance with the operation result. However, in case of a conditional

operation, they are not updated even though the specified condition is true and the operation is

executed. In case of an unconditional operation, they are always updated in accordance with the

operation result. The definition of a DC bit is selected by CS[2:0] (condition selection) bits in

DSR. The DC bit result is as follows:

Carry or Borrow Mode: CS[2:0] = 000: The DC bit indicates that carry or borrow is generated

from the most significant bit of the operation result, except the guard-bit parts. Some examples are

shown in figure 3.11. This mode is the default condition. When the input data is negative in a

PABS or PNEG instruction, carry is generated.

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