SH7713 datasheet(151/904 Pages) RENESAS

tên linh kiện	SH7713

Giải thích chi tiết về linh kiện	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 111 of 860

REJ09B0288-0150

The DSR is assigned to the system registers. For the DSR, the following load and store

instructions are supported.

STS DSR,Rn;

STS.L DSR,@-Rn;

LDS Rn,DSR;

LDS.L @Rn+,DSR;

If the DSR is read by the STS instruction, upper bits (bits 31 to 16) are all 0

3.5.2

DSP Operation Instruction Set

DSP operation instructions are instructions for digital signal processing performed by the DSP

unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed

in parallel. The instruction code is divided into an A field and B field; a parallel data transfer

instruction is specified in the A field, and a single or double data operation instruction in the B

field. Instructions can be specified independently, and are also executed independently.

B-field data operation instructions are of three kinds: double data operation instructions,

conditional single data operation instructions, and unconditional single data operation instructions.

The formats of the DSP operation instructions are shown in table 3.17. The respective operands

are selected independently from the DSP registers. The correspondence between DSP operation

instruction operands and registers is shown in table 3.18.

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