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SH7713 bảng dữ liệu(PDF) 148 Page - Renesas Technology Corp |
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SH7713 bảng dữ liệu(HTML) 148 Page - Renesas Technology Corp |
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148 / 904 page ![]() Section 3 DSP Operating Unit Rev.1.50 Aug. 30, 2006 Page 108 of 860 REJ09B0288-0150 Table 3.15 Source Register in DSP Operations Guard Bits Register Bits Registers Instructions 39 32 31 16 15 0 Fixed-point, PDMSB, PSHA 40-bit data Integer 24-bit data DSP operation Logical, PSHL, PMULS 16-bit data MOVX/Y.W, MOVS.W 16-bit data A0, A1 Data transfer MOVS.L 32-bit data MOVS.W Data A0G, A1G Data transfer MOVS.L Data Fixed-point, PDMSB, PSHA Sign* 32-bit data Integer Sign* 16-bit data DSP operation Logical, PSHL, PMULS 16-bit data MOVS.W 16-bit data X0, X1 Y0, Y1 M0, M1 Data transfer MOVS.L 32-bit data Note: * The data is sign-extended and input to the ALU. The DSP unit incorporates one control register and DSP status register (DSR). The DSR register stores the DSP data operation result (zero, negative, others). The DSP register also has the DC bit whose function is similar to the T bit of the CPU register. The DC bit functions as status flag. Conditional DSP data operations are controlled based on the DC bit. These operation control affects only the DSP unit instructions. In other words, these operations control affects only the DSP registers and does not affect address register update and CPU instructions such as load and store instructions. A condition to be reflected on the DC bit should be specified to the DC status selection bits (CS[2:0]). The unconditional DSP type data instructions other than PMULS, MOVX, MOVY, and MOVS change the condition flag and DC bit. However, the CPU instructions including the MAC instruction do not modify the DC bit. In addition, conditional DSP instructions do not modify the DSR. |
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