SH7713 datasheet(474/904 Pages) RENESAS

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 434 of 860

REJ09B0288-0150

that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle that

asserts the CKE in order to cancel power-down mode is inserted.

Figure 12.28 shows the access timing in power-down mode.

CKIO

A25 to A0

CSn

RD/

D31 to D0

Tnop

DACKn*2

Power-down

A12/A11*1

Tc1

Td1

Tde

Tap

Power-down

CKE

RAS

DQMxx

CAS

Notes: 1.Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 12.28 Access Timing in Power-Down Mode

Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed

after powering on. To perform synchronous DRAM initialization correctly, the bus state controller

registers must first be set, followed by a write to the synchronous DRAM mode register. In

synchronous DRAM mode register setting, the address signal value at that time is latched by a

combination of the

CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state

controller provides for value X to be written to the synchronous DRAM mode register by

performing a write to address H'A4FD4000 + X for area 2 synchronous DRAM, and to address

H'A4FD5000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the

mode write is performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3,

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