SH7713 datasheet(477/904 Pages) RENESAS

477 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 437 of 860

REJ09B0288-0150

CKIO

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

Tpw

DACKn*2

Trr

A12/A11*1

CAS

Notes: 1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Trc

Tmw

Hi-Z

Tnop

Trc

Trr

Trc

REF

MRS

PALL

Figure 12.29 Write Timing for SDRAM Mode Register (Based on JEDEC)

Low-Power SDRAM: The low-power SDRAM can be accessed using the same protocol as the

normal SDRAM. The differences between the low-power SDRAM and normal SDRAM are that

partial refresh takes place that puts only a part of the SDRAM in the self-refresh state during the

self-refresh function, and that power consumption is low during refresh under user conditions such

as the operating temperature. The partial refresh is effective in systems in which data in a work

area other than the specific area can be lost without severe repercussions. For details, refer to the

data sheet for the low-power SDRAM to be used.

The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode

registers as the normal SDRAM. This LSI supports issuing of the EMRS command.

The EMRS command is issued according to the conditions specified in table 12.20. For example,

if data H'0YYYYYYY is written to address H’A4FD5XXX in long-word, the commands are

issued to the CS3 space in the following sequence: PALL -> REF x 8 -> MRS -> EMRS. In this

case, the MRS and EMRS issue addresses are H'0000XXX and H'YYYYYYY, respectively. If

data H'1YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued

to the CS3 space in the following sequence: PALL -> MRS -> EMRS.

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