SH7708 datasheet(577/633 Pages) RENESAS

577 / 633 page

559

Table A.2

Pin Specifications (cont)

Pin No.

I/O

Function

D15 to D0

15 to 16,

21 to 29,

32 to 36

I/O

Data bus

CS6/CE1B

108

Chip select 6/PCMCIA

CS5/CE1A

109

Chip select 5/PCMCIA

CS4 to CS0

110 to 114

Chip select 4—chip select 0

105

Bus cycle start

RAS/CE

129

DRAM, synchronous DRAM

RAS/pseudo-SRAM CE

CASHH/CAS2H 119

D31–D24 (DRAM

CAS)/D15–D8 (area 2 DRAM CAS)

select signal

CASHL/CAS2L 120

D23-D16 (DRAM

CAS)/D7–D0 (area 2 DRAM CAS)

select signal

CASLH

125

D15–D8 select signal (DRAM

CAS)

CASLL/CAS/OE 126

D7–D0 select (DRAM

CAS)/memory select signal

(synchronous DRAM

CAS/pseudo-SRAM OE)

WE3/DQMUU/

ICIOWR

117

D31–D24 select signal (normal memory, pseudo-SRAM

WE/synchronous DRAM DQM)/IO write (PCMCIA,

PCMCIB)

WE2/DQMUL/

ICIORD

118

D23–D16 select signal (normal memory, pseudo-SRAM

WE/synchronous DRAM DQM)/IO write (PCMCIA,

PCMCIB)

WE1/DQMLU

123

D15–D8 select signal (normal memory, pseudo-SRAM

WE/synchronous DRAM DQM)

WE0/DQMLL

124

D7–D0 select signal (normal memory, pseudo-SRAM

WE/synchronous DRAM DQM)

RD/

106

Read/write (synchronous DRAM/DRAM/PCMCIA)

107

Read pulse (PCMCIA/normal memory)

WAIT

132

Hardware wait request

IOIS16

IO16 bit indication (PCMCIA IO area)

BREQ

Bus request

BACK

Bus acknowledge

IRQOUT

Interrupt request notification

RESET

Reset

Chip active

Causes a transition to hardware standby mode when

low. Drive high in a power-on reset.

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