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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SH7708 bảng dữ liệu(PDF) 516 Page - Renesas Technology Corp |
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SH7708 bảng dữ liệu(HTML) 516 Page - Renesas Technology Corp |
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516 / 633 page  498 17.3.1 Clock Timing Table 17.5 Clock Timing (VCC = 3.15Å–3.6 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 60 MHz) Item Symbol Min Max Unit Figure EXTAL clock input frequency fEX 5 60 MHz 17.1 EXTAL clock input cycle time tEXcyc 16.7 200 ns EXTAL clock input low-level pulse width tEXL 4*1 or 10*2 —ns EXTAL clock input high-level pulse width tEXH 4*1 or 10*2 —ns EXTAL clock input rise time tEXr —2 ns EXTAL clock input fall time tEXf —2 ns CKIO clock frequency (input) fCKI 16 60 MHz 17.2 CKIO clock cycle time (input) tCKIcyc 16.7 62.5 ns CKIO clock low-level pulse width (input) tCKIL 4— ns CKIO clock high-level pulse width (input) tCKIH 4— ns CKIO clock rise time (input) tCKIr —2 ns CKIO clock fall time (input) tCKIf —2 ns CKIO clock output frequency (output) fOP 16 60 MHz 17.3 CKIO clock cycle time (output) tcyc 16.7 62.5 ns CKIO clock low-level pulse width (output) tCKOL 3— ns CKIO clock high-level pulse width (output) tCKOH 3— ns CKIO clock rise time (output) tCKOr —5 ns CKIO clock fall time (output) tCKOf —5 ns Power-on oscillation settling time tOSC1 10 — ms 17.4 Power-on oscillation settling time/mode setting tOSCMD 10 — ms BREQ reset hold time tBREQRH 0— ns RESET set-up time tRESS 20 — ns BREQ set-up time tBREQS 20 — ns MD reset hold time tMDRH 20 — ns Reset assert time tRESW 20 — tcyc 17.4, 17.5, 17.11 Standby return oscillation settling time 1 tOSC2 10 — ms 17.5 Standby return oscillation settling time 2 tOSC3 10 — ms 17.6 Standby return oscillation settling time 3 tOSC4 11 — ms 17.7 PLL synchronization settling time tPLL 100 — µs 17.8, 17.9, 17.10 IRL interrupt decision time (using RTC and in standby mode) tIRLSTB 100 — µs 17.10 Notes: 1. PLL circuit 2 in operation. 2. IPLL circuit 2 not in operation. |
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