SH7243 datasheet(108/1726 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 78 of 1692

REJ09B0393-0100

4.3

Clock Operating Modes

Table 4.2 shows the clock operating modes of this LSI.

Table 4.2

Clock Operating Modes

Clock I/O

Mode

Source

Output

PLL Circuit

Input to Divider

EXTAL input or

crystal resonator

CK*

On (

× 8)

× 8

Note:

To output the clock through the CK pin, appropriate settings should be made in the

PFC. For details, refer to section 23, Pin Function Controller (PFC).

The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL

circuit before it is supplied to the on-chip modules in this LSI, which eliminates the need to

generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 10

MHz to 12.5 MHz can be used, the internal clock (I

φ) frequency ranges from 10 MHz to 100

MHz.

Maximum operating frequencies:

φ = 100 MHz, Bφ = 50 MHz, Pφ = 50 MHz, Mφ = 100 MHz, Aφ = 50 MHz

Table 4.3 shows the frequency division ratios that can be specified with FRQCR.

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